Re-added details of my USB 2.0 high speed (480mbps) capable bus capture device based on the miniSpartan6+ FPGA board….
A small bridge component to interface between a FTDI chip using the asynchronous FIFO mode (FT245R / FT2232) and an Opencores Wishbone master.
Also supports additional inputs and outputs for GPIO access.
This component (Verilog + PC side SW) allows reading and writing of memory (e.g. BRAM or SDRAM) via a FPGA at reasonably good speeds (I’ve measured > 5.4MB/s).
Developed and tested on MiniSpartan6+ board that I recently brought from Scarab HW.
The only gotcha is that you have to use the FT_PROG EEPROM programming tool from FTDI to switch the 2nd channel on the FT2232 to FT245 Async mode (there is a Windows tool available on FTDI’s website).
Component (RTL + SW):
Test Project (for the LX9 based minispartan6+):
The USB device Verilog + SW from the XC6BP project are now available at opencores.org under the LGPL license.
A FPGA based design with a soft CPU and USB device interface implemented in Verilog.
This design uses an OpenRISC compatible CPU (my AltOR32 implementation) running at 48MHz (a convenient speed for USB) and features cut-down USB 1.1 (Full Speed), SPI and GPIO interfaces.
A small USB stack implements a virtual serial port over USB, but could be extended to support other class drivers such as Audio or HID.
This board is form factor compatible with the Bus Pirate v3.5 case (see details of the real Bus Pirate here).
– Xilinx XC6SLX9
– SPI Flash (for FPGA configuration & additional code storage)
– Microchip 23LC1024 SPI RAM (128KBytes)
– USB transceiver (USB1T11A)
– 6MHz Oscillator
– 1.2v and 3.3V LDOs
The Spartan XC6SLX9 contains 64KBytes of usable blockRAM, some of which is used for internal code & RAM, as well as the CPU’s instruction cache and USB endpoint FIFOs.
Code, schematics & RTL available here (fpga_xc6bp.tar)…
Yet another Raspberry PI expansion module. This one’s purpose is to host a Spartan 6 FPGA, in-order to serve as a soft processor development environment.
Sitting on top of the PI’s 26-way P1 connector, it contains a Xilinx XC6SLX9 FPGA, 8MBit SPI Flash, 2 x 1Mbit SPI RAM, and a 10 way expansion connector.
The 1430 slice / 11,440 flop FPGA is large enough to hold my AltOR32 OpenRisc implementation (running at ~60MHz) along with instruction & data cache, debug interface to the PI, and with plenty of free space remaining.
The Spartan XC6SLX9 contains 64KBytes of usable blockRAM, some of which has been sacrificed for the CPU’s caches.
The board contain two Microchip 23LC1024 SPI RAMs, providing 256KBytes of additional memory mapped (and cacheable!) instruction or data space.
These RAMs are accessed in 4-bit SQI mode for increased data throughput.
The Raspberry PI is able to load the FPGA bitstream in around 1 second, and is then used to load the FPGAs internal or external memory for program execution.
You can also stop the program, inspect and modify CPU registers, memory, etc.
The CPU core benchmarks at roughly ~0.93DMIPS/MHz, which @ 60MHz is at least 16x lower than the ARM on the Raspberry PI at its stock frequency!
Still, there are plenty of interesting things you can do in HW on the FPGA that it will beat the PI at.
The core of the project, AltOR32 is also available on OpenCores.
AltOR32 is an alternative OpenRISC 1000 architecture derived RISC CPU which only implements the essential OpenRISC instructions and is targeted at smaller FPGAs.
This core makes use of the stock OpenRISC GCC port, but omits the vector, floating-point, 64-bit extensions & hardware multipliers / division.
AltOR32 easily fits on the Papilio One 250K (XC3S250E), and comes in pipelined & multi-cycle versions.
The Papilio One 250K port contains a Bootloader (with SPI PROM programmer), UART, Timers & GPIO and can run at over 40MHz.
The source, example FPGA project & bit files are available at OpenCores
‘MPX’ is a 32-bit soft-core pipelined RISC processor written in Verilog.
The processor implements the majority of MIPS-I™ ISA excluding the formally patented unaligned load/store instructions & also the hw multiplier / divider (mult, multu, div, divu) instructions.
Missing instructions can be resolved at compile time using a modified build of GCC or by generating traps at runtime on encountering the unsupported instructions.
The Papilio One 250K FPGA board is an excellent low cost development board containing a Xilinx XC3S250E and plenty of I/O ports (there is a XC3S500E version available too).
The Papilio XC3S250E port of MPX contains a Bootloader, support for GPIOs, UART & timers, and runs at 40MHz.
The source, example FPGA project (in VHDL) & FPGA bit files are available at OpenCores
The core was also used in the FPGA-Audio MP3/WAV player project here…
Just started writing up my FPGA based MP3 player project.
Added FAT16/32 IO Library article & download…