‘MPX’ is a 32-bit soft-core pipelined RISC processor written in Verilog.
The processor implements the majority of MIPS-I™ ISA excluding the formally patented unaligned load/store instructions & also the hw multiplier / divider (mult, multu, div, divu) instructions.

Missing instructions can be resolved at compile time using a modified build of GCC or by generating traps at runtime on encountering the unsupported instructions.

The Papilio One 250K FPGA board is an excellent low cost development board containing a Xilinx XC3S250E and plenty of I/O ports (there is a XC3S500E version available too).

The Papilio XC3S250E port of MPX contains a Bootloader, support for GPIOs, UART & timers, and runs at 40MHz.

The source, example FPGA project (in VHDL) & FPGA bit files are available at OpenCores

The core was also used in the FPGA-Audio MP3/WAV player project here…