AltOR32 OpenRISC ISA CPU on Papilio One 250K FPGA Board

AltOR32 is an alternative OpenRISC 1000 architecture derived RISC CPU which only implements the essential OpenRISC instructions and is targeted at smaller FPGAs.

This core makes use of the stock OpenRISC GCC port, but omits the vector, floating-point, 64-bit extensions & hardware multipliers / division.

AltOR32 easily fits on the Papilio One 250K (XC3S250E), and comes in pipelined & multi-cycle versions.

The Papilio One 250K port contains a Bootloader (with SPI PROM programmer), UART, Timers & GPIO and can run at over 40MHz.

The source, example FPGA project & bit files are available at OpenCores

3 Responses to “AltOR32 OpenRISC ISA CPU on Papilio One 250K FPGA Board”

  • How many memory are you using ?

    Were you able to run any “large” program ? I recall trying OpenRISC but it was large, low MHZ and quite some overhead for code size.

    • The current OpenRISC OR1K ISA only supports 32-bit instructions, so yes, code size is an issue in small FPGA (as you know, the XC3S250E only really has 24KBytes of useful blockRAM).
      You can of course choose to execute code direct from the SPI Flash configuration PROM, if you choose to write some RTL to allow such a thing (as I have).
      With a 512KB SPI Flash, 384KB of which is used for the FPGA bitstream, this leaves 128KB of program code space (ROM).
      With a small cache to improve execution speed from the serial flash, you could conceivably end up with 128KB ROM, 16KB RAM and a 32-bit CPU running at ~50MHz in a small FPGA such as the Spartan 3 250E.

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