FTDI to Wishbone Bridge

A small bridge component to interface between a FTDI chip using the asynchronous FIFO mode (FT245R / FT2232) and an Opencores Wishbone master.
Also supports additional inputs and outputs for GPIO access.

This component (Verilog + PC side SW) allows reading and writing of memory (e.g. BRAM or SDRAM) via a FPGA at reasonably good speeds (I’ve measured > 5.4MB/s).
Developed and tested on MiniSpartan6+ board that I recently brought from Scarab HW.

The only gotcha is that you have to use the FT_PROG EEPROM programming tool from FTDI to switch the 2nd channel on the FT2232 to FT245 Async mode (there is a Windows tool available on FTDI’s website).

Requires libftdi-dev.

Component (RTL + SW):
https://github.com/ultraembedded/cores/tree/master/ftdi_async_bridge

Test Project (for the LX9 based minispartan6+):
https://github.com/ultraembedded/minispartan6/tree/master/sdram_ftdi_test

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