A FPGA based design with a soft CPU and USB device interface implemented in Verilog.
This design uses an OpenRISC compatible CPU (my AltOR32 implementation) running at 48MHz (a convenient speed for USB) and features cut-down USB 1.1 (Full Speed), SPI and GPIO interfaces.
A small USB stack implements a virtual serial port over USB, but could be extended to support other class drivers such as Audio or HID.
This board is form factor compatible with the Bus Pirate v3.5 case (see details of the real Bus Pirate here).
– Xilinx XC6SLX9
– SPI Flash (for FPGA configuration & additional code storage)
– Microchip 23LC1024 SPI RAM (128KBytes)
– USB transceiver (USB1T11A)
– 6MHz Oscillator
– 1.2v and 3.3V LDOs
The Spartan XC6SLX9 contains 64KBytes of usable blockRAM, some of which is used for internal code & RAM, as well as the CPU’s instruction cache and USB endpoint FIFOs.
Code, schematics & RTL available here (fpga_xc6bp.tar)…