XC6BP – FPGA Based 'Bus Pirate'

A FPGA based design with a soft CPU and USB device interface implemented in Verilog.
This design uses an OpenRISC compatible CPU (my AltOR32 implementation) running at 48MHz (a convenient speed for USB) and features cut-down USB 1.1 (Full Speed), SPI and GPIO interfaces.

A small USB stack implements a virtual serial port over USB, but could be extended to support other class drivers such as Audio or HID.

This board is form factor compatible with the Bus Pirate v3.5 case (see details of the real Bus Pirate here).

Minimal components;
– Xilinx XC6SLX9
– SPI Flash (for FPGA configuration & additional code storage)
– Microchip 23LC1024 SPI RAM (128KBytes)
– USB transceiver (USB1T11A)
– 6MHz Oscillator
– 1.2v and 3.3V LDOs

The Spartan XC6SLX9 contains 64KBytes of usable blockRAM, some of which is used for internal code & RAM, as well as the CPU’s instruction cache and USB endpoint FIFOs.

Code, schematics & RTL available here (fpga_xc6bp.tar)…

XC6BP (top)

3 thoughts on “XC6BP – FPGA Based 'Bus Pirate'

  1. Olof Kindgren


    This is awesome work. I’ve been having the same idea for a few years, but using a de0 nano instead of a custom board, and using or1200 or mor1kx instead of AltOr32.

    I see now that a custom board is much better, and it’s fun to see AltOr32 in action. It would be very interesting to have you come and talk (or just show off the boards) at the next OpenRISC conference.

    Are you planning to sell the boards, btw? I’ve been thinking about getting myself a bus pirate for some time, but this would be even more fun and useful


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